1. Field of the Invention
This invention relates generally to impedance matching circuits, and more particularly, to a digital compensation scheme for reducing delay in a digital impedance matching circuit to improve return loss.
2. Description of the Prior Art
Impedance matching is a critical function for telephone equipment. The trend for telephone line impedance matching has been from hybrid transformer to discrete opamp circuits, to integrated analog/digital implementations used to synthesize the required matching impedance.
Digital implementations of impedance matching networks are problematic due to the delay(s) through the digital processor(s). These delays cause a phase difference between the incident and synthesized signals which results in an amplitude difference that worsens the Return Loss. This problem is generally alleviated by using a faster, but more costly and higher power consuming digital converter and processor.
In view of the foregoing, it would be desirable and advantageous to provide a simple, power efficient and inexpensive digital compensation scheme for reducing delay in a digital impedance matching circuit to improve return loss.